Case Study: The Broken Link (JTAG & Boundary Scan) Case Study: The Broken Link How JTAG and Boundary Scan Test the "Untestable" Board 1. Introduction: The "It-Works-Alone" Problem Our DFT journey so far has been inside the chip. We've used Scan, MBIST, and At-Speed tests to gain 99.9% confidence that the *silicon die itself* is perfect. This "perfect" chip is then packaged (e.g., in a Ball Grid Array (BGA) ) and soldered to a Printed Circuit Board (PCB) alongside other chips (like DRAM, a Wi-Fi module, etc.). The system is assembled, powered on, and... it's dead. We have a new, critical problem: The CPU chip is perfect. The DRAM chip is perfect. ...